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Ordering number : EN*4435A
CMOS LSI
LC587008, 587006, 587004
Single-Chip 4-Bit Microprocessors with LCD Driver, 2 Kb RAM, and 8, 12, or 16 KB ROM on chip
Preliminary Overview
The LC587004, LC587006 and LC587008 are 80-pin lowvoltage CMOS 4-bit microprocessors that include LCD drivers, 2 Kb RAM and 8, 12, or 16 KB ROM on chip. These microprocessors correspond to the earlier LC5870 series with the 256 by 4-bit on-chip RAM expanded to a 512 by 4-bit capacity. * Powerful hardware for improved processing capacity -- Built-in segment PLA and segment decoder: LCD panel segments can be handled with no software processing of the LCD driver outputs. Also, the LCD drive pins can be switched to function as output ports. -- Built-in 8-bit synchronous serial I/O circuit -- One 8-bit programmable timer (that can be used as an event counter) -- One 8-bit programmable reload timer (that can be used to generate a remote control carrier signal) -- The whole RAM area can be used as working area (by using the RAM bank register) -- Built-in RAM data pointer -- Built-in clock oscillator and 15-bit divider (also used to generate the LCD alternating frequency) * Highly flexible LCD panel drive output pins (35 pins) LCD panel ................Number of ...........Required drive type...................segments ..............common pins 1/3 bias 1/4 duty ........140 segments .......Four pins 1/3 bias 1/3 duty ........105 segments .......Three pins 1/2 bias 1/4 duty ........140 segments .......Four pins 1/2 bias 1/3 duty ........105 segments .......Three pins 1/2 bias 1/2 duty ........70 segments .........Two pins Static..........................35 segments .........One pin The LCD output pins can be switched to function as general-purpose outputs. -- C-MOS type: Up to 35 pins -- P-channel type: Up to 35 pins -- N-channel type: Up to 35 pins * These microprocessors allow the use of an oscillator appropriate to the application system specifications. -- Crystal oscillator: 32 kHz, 65 kHz or 38 kHz (for the time base, system clock or LCD alternating frequency) -- Ceramic oscillator: 400 kHz to 4 Mhz (for the system clock and the timers and serial counter) -- RC oscillator: 200 kHz to 1 MHz (for the system clock and the timers and serial counter) -- External clock (for the system clock and the timers and serial counter)
Applications
* System control and LCD display in CD players, cameras and radio tuners * System control and LCD display in miniature test equipment and consumer health care products * These microprocessors are optimal for products that include LCD displays and, in particular, battery operated products. * Remote controllers for VCRs and audio equipment
Functions
* Program ROM: 8064 x 16 bits (LC587008), 6144 x 16 bits (LC587006) and 4096 x 16 bits (LC587004) * RAM: 512 x 4 bits on chip * All instructions execute in a single cycle * Cycle time and operating voltage ranges -- 2 s cycle time: VDD = 2.8 to 6.0 V 10 s cycle time: VDD = 2.2 to 6.0 V 122 s cycle time: VDD = 2.0 to 6.0 V * Rich set of HALT/HOLD mode clearing and interrupt functions -- Eight HALT mode clearing functions -- Seven HOLD mode clearing functions -- Seven interrupt functions (all of which can be used as external interrupts) -- Subroutines can be nested up to eight levels (including interrupt handling) -- Built-in watchdog timer function
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63095HA (OT)/N1194JN/D1192JN No. 4435-1/29
LC587008, 587006, 587004
Features
* These microprocessors are the top end of the LC5870 series and have the following features. Faster cycle times -- Cycle time: 2 s for VDD between 4.5 and 6.0 V -- Cycle time: 10 s for VDD between 2.2 and 6.0 V Low power dissipation HALT mode (typical) Continuous operation (typical) -- Ceramic filter (CF) 4 MHz (5.0 V) 600 A 1.7 mA (cycle time = 2 s) -- Crystal oscillator 32 kHz (3.0 V, CF stopped) 4.0 A 20 A (cycle time = 122 s) Improved timer functions -- One 8-bit programmable timer (that can be used as an event counter) -- One 8-bit programmable reload timer (that can be used to generate a remote control carrier signal) -- Time base timer (for use as a clock) -- Watchdog timer Improved standby functions -- Clock standby function (HALT mode), software switching between low speed mode (low current) and high speed mode -- Full standby mode (HOLD mode) -- HALT and HOLD modes can be cleared by external interrupt pins, input ports (up to nine pins) and serial I/O interrupts Improved I/O functions -- External interrupt pins -- Up to 9 input and I/O pins that can clear HALT and HOLD modes -- Up to 24 input ports with built-in software controllable input resistors (either pull-up or pulldown specified as mask options) -- Up to 25 input port pins with a built-in floating prevention circuit -- LCD driver: four common pins and 35 segment pins -- General-purpose I/O ports: 20 pins (of which 12 are p-channel open drain and 4 are n-channel open drain) -- General-purpose inputs: five pins -- General-purpose outputs (type 1): four pins (LED direct drive pins, one internal alarm signal output pin and one carrier output pin) -- General-purpose outputs (type 2): 35 pins (when all 35 LCD segment port pins are switched over to function as general-purpose outputs) -- Eight-bit serial I/O port: one set (three pins: input, output and clock) * Delivery formats: QFP80 (QIP80) and chip
Package Dimensions
unit: mm 3044B-QFP80A
[LC587008, 587006, 587004]
SANYO: QIP80A
No. 4435-2/29
LC587008, 587006, 587004 Pad Layout Chip size: 5.12 mm x 5.29 mm Pad size: 120 m x 120 m Chip thickness: 480 m (chip products)
Pin Assignments/Pad Names and Coordinates
Pin Pad No. No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol VDD CFIN CFOUT S1 S2 S3 S4 K1 K2 K3 K4 M1 M2 M3 M4 N1 N2 N3 N4 TST Seg 1 Seg 2 Seg 3 Seg 4 Seg 5 Seg 6 Seg 7 Seg 8 Coordinates Xm 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 2234 1958 1732 1506 1280 1054 874 694 514 335 Ym -2319 -1883 -1701 -1458 -1212 -915 -669 -284 -101 81 264 448 631 814 997 1352 1624 1895 2173 2449 2449 2449 2449 2449 2449 2449 2449 2449 Pin Pad No. No. 52 53 54 55 56 57 58 59 60 61 62 -- -- 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol Seg 9 Seg 10 Seg 11 Seg 12 Seg 13 Seg 14 Seg 15 Seg 16 Seg 17 Seg 18 Seg 19 Test Test Seg 20 Seg 21 Seg 22 Seg 23 Seg 24 Seg 25 Seg 26 Seg 27 Seg 28 Seg 29 Seg 30 Seg 31 Seg 32 Seg 33 Seg 34 Coordinates Xm 155 -24 -204 -384 -564 -744 -923 -1103 -1283 -1463 -1643 -1821 -2001 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 -2362 Ym 2449 2449 2449 2449 2449 2449 2449 2449 2449 2449 2449 2449 2449 2449 2248 1649 1468 1288 1107 799 618 438 257 77 -103 -283 -464 -664 Pin Pad No. No. 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Symbol Seg 35 COM4 COM3 COM2 COM1 CUP1 CUP2 RES INT SO1 SO2 SO3 SO4 A1 A2 A3 A4 P1 P2 P3 P4 XTOUT XTIN VDD2 VDD1 VSS Coordinates Xm -2362 -2362 -2362 -2362 -1912 -1730 -1549 -1327 -1145 -963 -780 -597 -414 -231 -48 134 317 504 687 870 1053 1279 1462 1685 1868 2050 Ym -824 -1139 -1564 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319 -2319
Input port
I/O port
I/O port, SIO port
I/O port
I/O port
Output port
I/O port
Note: 1. 2. 3. 4. 5.
Pin numbers are for QIP80 package products. Connect the test pins (TST) to VSS. Pad numbers 40 and 41 must be left open in the chip specification product. Do not use dip-soldering techniques to mount the QIP80 package versions. For chip products either connect the substrate to VSS or leave it open.
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LC587008, 587006, 587004 System Block Diagram
System Block Diagram for the LC587008, LC587006 and LC587004 RAM: ROM: DP: BNK: APG: AC: ALU: B: OPG: PC: Data memory Program memory Data pointer register Bank register RAM page flags Accumulator Arithmetic and logic unit B register ROM page flag Program counter IR: STS1: STS2: STS3: STS4: STS5: PLA: Instruction register Status register 1 Status register 2 Status register 3 Status register 4 Status register 5 Segment data and strobe programmable logic array WAIT.C: Waiting time counter
No. 4435-4/29
LC587008, 587006, 587004 Pin Functions
Pin VDD VSS I/O -- -- QIP-80 Pin No. 24 23 Power supply LCD drive power supply Function Option At reset
VDD1 VDD2
-- --
22 21
CUP1 CUP2
-- --
3 4
Switching pin used to supply the LCD drive voltage to the VDD1 and VDD2 pins * Connect a nonpolarized capacitor between CUP1 and CUP2 when 1/2 or 1/3 bias is used. * Leave open when a bias other than 1/2 or 1/3 is used. System clock oscillator connections * Ceramic resonator connection (CF specifications) * RC component connection (RC specifications) * External signal input pin (CFOUT is left open) This oscillator is stopped by the execution of a STOP or SLOW instruction. Reference calculation (clock specifications, LCD alternating frequency), system clock oscillator * 32 kHz crystal resonator connection * 65 kHz crystal resonator connection This oscillator is stopped by the execution of a STOP instruction. Input-only ports * Input pins used to read data into RAM * Built-in 7.8 ms and 1.95 ms chatter rejection circuits * Built-in pull-up/pull-down resistors Note: The 7.8 ms and 1.95 ms times are the times when o0 is 32.768 kHz. * CF specifications * RC specifications * External specifications * Not used
CFIN
Input
25
CFOUT
Output
26
XTIN
Input
20
XTOUT
Output
19
* * * *
32k specifications 65k specifications 38k specifications Not used * The pull-up or pulldown resistors are on. Note: These pins go to the floating state when reset is cleared. * The pull-up or pulldown resistors are on. Note: These pins go to the floating state when reset is cleared. * Input mode * Output latch data is set high.
S1 S2 S3 S4
Input
27 28 29 30
* Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors
K1 K2 K3 K4
I/O
31 32 33 34
I/O ports * Input pins used to read data into RAM * Output pins used to output data from RAM * Built-in 7.8 ms and 1.95 ms input-mode chatter rejection circuits. The selection of 7.8 or 1.95 ms is linked to that for the S ports. Note: The 7.8 ms and 1.95 ms times are the times when o0 is 32.768 kHz. I/O ports * Input pins used to read data into RAM * Output pins used to output data from RAM * M4 is used as the external clock input pin in TM2 mode 3. * The minimum period for the external clock is twice the cycle time. * Built-in pull-up/pull-down resistors I/O ports * Input pins used to read data into RAM * Output pins used to output data from RAM * Built-in pull-up/pull-down resistors I/O ports Function: The same as pins A1 to A4
* Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors
M1 M2 M3 M4 A1 A2 A3 A4 P1 P2 P3 P4
I/O
35 36 37 38 11 12 13 14 15 16 17 18
The same as K1 to K4
The same as K1 to K4
I/O
The same as K1 to K4
The same as K1 to K4
I/O
The same as K1 to K4
The same as K1 to K4
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QIP-80 Pin No.
Pin
I/O
Function I/O ports Function: The same as for pins A1 to A4 Pins SO1 to SO3 area also used for the serial interface. * Use of these pins in serial mode can be selected under program control. * Pin functions: SO1: Serial input pin SO2: Serial output pin SO3: Serial clock pin The serial clock pin can be switched between internal and external, and between rising edge output and falling edge output. Output-only ports * Output pins used to output data from RAM * An alarm signal can be output from pin N4. (Note that this is only when the N4 output latch is low.) * An alarm signal modulated at 1, 2 or 4 kHz can be output. (These frequencies are output when o0 is 32.768 kHz.) * A carrier signal can be output from N3. (Note that this is only when the N3 output latch is low.)
Option * Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors * Internal serial clock divisor selection I 1/1 II 1/2 III 1/4 * Pins N1 to N4 output circuit type: I CMOS II N-channel open drain * Pins N1 to N4 output level I High level II Low level * Transistors to hold a low or high level * Selection of either pull-up or pulldown resistors * Signal conversion (rising/falling) selection * Only when the input resistor open specification is selected
At reset
SO1 SO2 SO3 SO4
I/O
7 8 9 10
The same as for K1 to K4
N1 N2 N3 N4
Output
39 40 41 42
The output levels on pins N1 to N4 can be specified as an option.
INT
Input
6
Input ports * External interrupt request inputs * Input pins used to read data into RAM * Input detection can be performed on either rising or falling edges. * Built-in pull-up/pull-down resistors LSI internal reset input * The reset input level can be selected to be either high or low. * Built-in pull-up/pull-down resistors * Note: The reset pulse must be at least 500 s. Test input * QIP80 products: Connect to VSS. * Chip products: Leave open or connect to VSS.
RES
Input
5
TST
Input
43
Seg1, Seg2 to Seg35
Output
44, 45 to 78
* LCD panel drive/general-purpose output -- LCD panel drive I STATIC II 1/2 bias - 1/2 duty III 1/2 bias - 1/3 duty IV 1/2 bias - 1/4 duty V 1/3 bias - 1/3 duty VI 1/3 bias - 1/4 duty Types I to V can be specified as mask options. -- General-purpose output mode I CMOS II P-channel open drain III N-channel open drain Types I to III can be specified as mask options. * LCD/general-purpose output control is handled by the segment PLA, and thus program control is not required. * These pins support output latch control on reset and in standby states when the oscillators are stopped. * Arbitrary combinations of LCD drive and general-purpose outputs can be used.
* LCD driver/ general-purpose output switching * LCD drive type switching -- STATIC -- 1/2 bias - 1/2 duty -- 1/2 bias - 1/3 duty -- 1/2 bias - 1/4 duty -- 1/3 bias - 1/3 duty -- 1/3 bias - 1/4 duty * General-purpose output circuit switching -- CMOS -- P-channel open drain -- N-channel open drain * Output latch control in standby modes
* LCD drive -- All segments on -- All segments off *: Determined by mask options * General purpose outputs -- High level -- Low level *: Determined by mask options Note: When a combination of LCD drive and generalpurpose outputs, the output state is either: -- All lit/high level -- All off/low level. * These pins go to the static drive mode during the reset period.
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LC587008, 587006, 587004
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QIP-80 Pin No.
Pin
I/O
Function LCD panel drive common polarity outputs The table below shows how these pins are used depending on the duty used. (Values for alternating frequency reflect a typical specification of 32.768 MHz for o0.)
Option
At reset The static drive waveform is output during the reset period. * There are cases where the alternating frequency stops for the CF, RC and external clock specifications. (These cases differ depending on option specifications.)
COM1 COM2 COM3 COM4
Output
2 1 80 79
Static duty COM1 COM2 COM3 COM4 Alternation frequency ! ! ! 32 Hz
1/2 duty
1/3 duty
1/4 duty
! ! 32 Hz
! 42.7 Hz 32 Hz
Note: A cross ( ! ) indicates that the pin is not used with that duty type.
Sample Application Circuit LCD: 1/2 bias - 1/4 duty
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LC587008, 587006, 587004 Oscillator Circuit Options
Option Circuit configuration Note
RC and Xtal
* The cycle time is four times the f1 period. * The divider outputs (o1 to o15) are used as the time base, the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions. * OSC1 is stopped when a SLOW instruction is executed.
CF and Xtal * 400 kHz (CF) * 4 MHz (CF)
* The cycle time is four times n times the f1 period. (Note: n is 2.) * The divider outputs (o1 to o15) are used as the time base, the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions. * OSC1 is stopped when a SLOW instruction is executed.
RC
* The cycle time is four times the f1 period. * The divider outputs (o1 to o15) are used as the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.
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LC587008, 587006, 587004
Continued from preceding page.
Option Circuit configuration Note
CF * 400 kHz * 4 MHz
* The cycle time is four times n times the f1 period. (Note: n is 2.) * The divider outputs (o1 to o15) are used as the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.
Xtal
* The cycle time is four times the f2 period. * The divider outputs (o1 to o15) are used as the time base, the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.
External input
* The cycle time is four times n times the f1 period. (Note: n is 2.) * The divider outputs (o1 to o15) are used as the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions.
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LC587008, 587006, 587004 Crystal Oscillator Circuit Options
Option Circuit configuration Note
32 kHz oscillator
The resistor Rd (200 k typical) for use with a 32 kHz oscillator is built in.
5 kHz oscillator 38 kHz oscillator
* The cycle time is four times n times the f1 period. (Note: n is 2.) * The divider outputs (o1 to o15) are used as the time base, the LCD drive waveform generation clock, the S and K port chattering rejection clock and for other functions. * OSC1 is stopped when a SLOW instruction is executed.
Input Port Options
Option Circuit configuration Note
Selection of either the * Built-in pull-up resistor, or the * Built-in pull-down resistor option
The following ports are switched at the same time * S1 to S4, K1 to K4, M1 to M4, P1 to P4 SO1 to SO4 and A1 to A4 At reset: The resistors are on during the reset period. The resistors are turned off when reset is cleared. Options: Either A or B can be selected. One of A and B must be selected.
Selection of high or low level hold transistor
Combination examples Type Pull-up resistor (A) Pull-down resistor (B) High level hold transistor (C) Low level hold transistor (D) On On 1 On 2 On On On 3 4
When the hold transistors used option is selected: * Used to reduce the current flowing in the pull-up or pull-down resistors when, for example, a push switch is used for S1 or a slide switch is used for S2. * For input open specification versions, the resistors are turned on before the input is read, the input state is read and then the resistors are turned off. If the input is floating at this point the high or low level hold transistor operates to hold the value read. When the hold transistors unused option is selected: * Use with the pull-up or pull-down resistor in the on state. * Select hold transistors unused when connecting to external control signals and the connections will never be floating
No. 4435-10/29
LC587008, 587006, 587004 INT Pins
Option Circuit configuration Note
Pull-up resistor, pulldown resistor or resistor open selection
Built-in resistor selection * Pull-up resistor used * Pull-down resistor used * Used open
High or low level hold transistor selection
Input signal level hold transistor selection * High level hold transistor used * Low level hold transistor used * Level hold transistors unused
Rising edge or falling edge detection selection
Signal change edge detection switching * Change on rising signal * Change on falling signal
RES Pin
Option Circuit configuration Note
Pull-up resistor, pulldown resistor or resistor open and reset level selection
Built-in resistor and polarity selection * Pull-up resistor connected, low level reset * Pull-down resistor connected, high level reset * Resistors open, low level reset * Resistors open, high level reset
Pins N1 to N4
Option Circuit configuration Note
N-channel/CMOS selection
* Selection of CMOS or n-channel open drain circuit type * Pins N1 to N4 can be specified independently * The output level during reset can be specified. -- High level -- Low level
No. 4435-11/29
LC587008, 587006, 587004 Fifteen-Stage Divider Overflow Time
Option Circuit configuration Note
* 1000 ms/250 ms * 500 ms/125 ms
A 15-stage (15-bit) divider is provided on chip to count the reference time. One of two types of divider overflow detection can be selected as a mask option and a further selection of two types can be made under program control. One of these mask options must be specified.
K Input Port Options
Option Circuit configuration Note
Pull-up/pull-down resistor selection
When the pull-up/pull-down resistor selection is made, the K port input detection switching gate is switched accordingly. A: When all of K1 to K4 are high and even one pin goes low a signal is applied to the edge detection circuit. (Applies to the pullup specifications.) Note: When even one of the K1 to K4 pins is low, the edge detection circuit will not operate for any combination of high or low values on the other pins. B: The opposite of item A
No. 4435-12/29
LC587008, 587006, 587004 Mask Option Overview 1. Port resistor selection (ports S, K, P, M, A and SO) * Pull-up resistor specification * Pull-down resistor specification 2. S port high or low level hold transistors * Level hold transistors used * No level hold transistors 3. K port high or low level hold transistors * Level hold transistors used * No level hold transistors 4. M port high or low level hold transistors * Level hold transistors used * No level hold transistors 5. P port high or low level hold transistors * Level hold transistors used * No level hold transistors 6. A port high or low level hold transistors * Level hold transistors used * No level hold transistors 7. SO port high or low level hold transistors * Level hold transistors used * No level hold transistors 8. INT pin resistor selection and signal edge selection * Pull-up resistor (negative edge) * Pull-down resistor (positive edge) * Open (negative edge) * Open (positive edge) 9. INT pin level hold transistor selection * Low or high level hold transistors used * No low or high level hold transistors 10. RES pin * Pull-up resistor (low level reset) * Pull-down resistor (high level reset) * Open (low level reset) * Open (high level reset) 11. N1 pin * N-channel open drain type * CMOS type 12. N2 pin * N-channel open drain type * CMOS type 13. N3 pin * N-channel open drain type * CMOS type
No. 4435-13/29
LC587008, 587006, 587004 14. N4 pin * N-channel open drain type * CMOS type 15. N port initial level * High level * Low level 16. OSC specifications * CF only (ceramic filter) * RC only (resistor and capacitor oscillator) * Crystal only (32 to 65 kHz crystal oscillator) * CF + crystal * RC + crystal * External + crystal 17. CF/External * 400 kHz or 800 kHz * 1 MHz, 2 MHz or 4 MHz 18. Crystal oscillator * 32 kHz * 65 kHz * 38 kHz 19. Fifteen-bit counter overflow * o0/2048 or o/8192 * o0/4096 or o0/16384 20. Serial I/O internal clock period * Cycle time x 1 x 2 * Cycle time x 2 x 2 * Cycle time x 4 x 2 21. LCD driver * Static * 1/2 bias - 1/2 duty * 1/2 bias - 1/3 duty * 1/2 bias - 1/4 duty * 1/3 bias - 1/3 duty * 1/3 bias - 1/4 duty 22. LCD alternating frequency * Slow * Typical * Fast 23. Internal reset circuit * Selection * Disabled 24. Segment ports at reset LCD drive pins * All on * All off CMOS, p/n-channel type pins * High level
No. 4435-14/29
LC587008, 587006, 587004 Internal Register Functions
Symbol R/W Function Initialization value at reset
Program counter The PC is a 13-bit counter that indicates the address in program memory (ROM) of the next instruction to execute. Normally the PC is incremented on every instruction cycle in the range 000H to 1F7FH. (Addresses in the range 1F80 to 1FFF are reserved for testing and cannot be used by user programs.) However, data values are loaded into the PC by the execution of branch and subroutine instructions and on the occurrence of interrupts or an initial reset. The table below describes the data loaded for these operations. PC Operation Initializing reset INT pin external interrupt S/K pin external interrupt PC -- Timer 1 or timer 2 internal interrupt Serial counter internal interrupt or SO4 pin external interrupt Unconditional jump (JMP) Conditional jump (BAB0, BAB1, BAB2, BAB3, BAZ, BANZ, BCH, BCNH) Call instruction (CALL) Return instruction (RTS, RTSR) Page: PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 0 0 Page Page Page 0 0 0 0 0 0 0 0 0 0 P10 P10 P10 0 0 0 0 0 P9 P9 P9 0 0 0 0 0 P8 P8 P8 0 0 0 0 0 P7 P7 P7 0 0 0 0 0 P6 P6 P6 0 1 1 1 1 P5 P5 P5 0 0 0 1 1 P4 P4 P4 0 0 1 0 1 P3 P3 P3 0 0 0 0 0 P2 P2 P2 0 0 0 0 0 P1 P1 P1 0 0 0 0 0 P0 P0 P0
CALL address + 1
the ROM page flags, which take 2048 locations as a single page The page is specified with the MROPF and SROPF instructions. P00 to P10: Bits in the instruction code (i.e., immediate data)
Program memory The ROM memory consists of 4096 x 16 bits (4 kwords or 8 kbytes) in the LC587004, 6144 x 16 bits (6 kwords or 12 kbytes) in the LC587006 and 8064 x 16 bits (8 kwords or 16 kbytes) in the LC587008. ROM hold user programs to be executed.
ROM
R/O
RAM
R/W
Data memory These microprocessors provide an on-chip RAM that consists of 512 x 4 bits (2 Kb). This RAM is accessed as two 256 x 4-bit pages. RAM addresses can be specified in four ways as listed below. * Directly specified at 00H to FFH (immediate addressing) * Indirect specification using the 8-bit data pointer. * Indirect specification by the 4-bit RAM bank register multiplied by 10H plus immediate data in the range 0 to FH. * Indirect specification by the 4-bit RAM bank register multiplied by 10H plus 8H plus immediate data in the range 0 to FH. Writing to RAM is always performed through the accumulator.
Undefined
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Symbol R/W Function Initialization value at reset
RAM
R/W
Undefined
Note: In case B, data pointer RAM address specification is illegal if the RAM address specification (the DPH immediate data) has the same value as the RAM bank register (BNK). In this case immediate specification is allowed. Example: If an IPS 10H instruction is executed when the data pointer flag is set, DPH is 5H, DPL is 3 H and the RAM bank register (BNK) is 1H, then the contents of the S port will be written to RAM location 10H. Example: If BNK and DPH differ, then the following operation will be performed. If an IPS 10H instruction is executed when DPF is 1, DPH is 5, DPL is 3 and BNK is 4, then the contents of the S port will be written to RAM location 53H.
Accumulator AC R/W Undefined
B register
B
R/W
Undefined
This register is used in combination with RAM as a pair for output to the LCD ports and for timer 2, serial counter and data pointer I/O. Data pointer
DP
R/W
Undefined
The data pointer register functions as a data pointer when the data pointer flag (DPF) is set, allowing control of the onchip RAM.
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Symbol R/W Function Stack pointer The stack consists of eight 14-bit registers and thus can be set to a depth of up to eight levels. The stack pointer is incremented by CALL instructions and interrupts, and decremented by RTS, RTSR and POP instructions. Initialization value at reset
STACK
R/W
01H
P0 to P11: Program counter (PC) DPF: Data pointer flag
Bank register The bank register is a 4-bit register that divides RAM (from 00H to FFH) into 16 sections and is used in moving RAM data, immediate operations and setting the data pointer.
BNK
R/W
00H
Example: ADD*_5,10.....If BNK is 6 then the operation performed will be: RAM(65H) + 10 AC RAM(65H).
APG
R/W
RAM page flags The RAM page flags consist of 2 bits that allow RAM to be expanded in 256 4-bit pages to a total of 1024 4-bit locations. Note: Pages 2 and 3 cannot be used by the LC587004, LC587006 and LC587008.
00H
Timer counters The timers consist of 8-bit down counters. (timer 1 and timer 2) Timer setting is performed in 8-bit units for immediate data. (timer 1 and timer 2) Reading and writing the lower 4 bits of a timer counter is performed through a RAM location. (timer 2 only) Reading and writing the upper 4 bits of a timer counter is performed using the B register. (timer 2 only)
TIM TIM1 TIM2
R/W
Undefined
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LC587008, 587006, 587004
Continued from preceding page.
Symbol R/W Function Serial counter The serial counter is an 8-bit shift register. Reading and writing the lower 4 bits of the serial counter is performed through a RAM location. Reading and writing the upper 4 bits of the serial counter is performed using the B register. Initialization value at reset
SIO
R/W
Undefined
OPG
R/W
ROM page flags The ROM page flags consist of 2 bits that allow ROM to be expanded in 2048 16-bit pages to a total of 8063 16-bit locations. In the LC587004 the legal values are 0 and 1, in the LC587006 the legal values are 0 to 2 and in the LC587008 the legal values are 0 to 3. (The operation when an illegal value is used is undefined.) Status register 1 (STS1) Status register 1 is a 4-bit register whose bits are used as shown below.
00H
STS1
R/O
00H
Status register 2 (STS2) Status register 2 is a 4-bit register that is used for serial counter control and state confirmation.
STS2
R/W
00H
ICF: High when the internal clock is used OSELF: High when the SO2 pin is set to the high impedance state (Z). Low when SO2 is set to the CMOS or n-channel open drain state. SIOF: High when used as serial I/O CSTF: High on serial counter start Low during serial counter operation
Continued on next page. No. 4435-18/29
LC587008, 587006, 587004
Continued from preceding page.
Initialization value at reset
Symbol
R/W
Function
Status register 3 (STS3) Status register 3 is a 4-bit register that is used to confirm the HALT and STOP clear conditions.
STS3
R/O
00H
SCF0: Set to 1 if there was a signal change on the INT pin. SCF1: Set to 1 if there was a signal change on the K port. SCF2: Set to 1 if any of the flags in STS4 is set. SCF3: Set to 1 if there was a signal change on the S port. Note: SCF0 is used when enabled by an SF2-1 instruction. SCF1 and SCF3 are used when enabled by an SSW instruction.
Status register 4 (STS4) Status register 4 is a 4-bit register that is used to confirm the HALT and STOP clear conditions.
STS4
R/O
00H
SCF4: Divider overflow SCF5: Timer 1 underflow SCF6: Timer 2 underflow SCF7: Serial counter overflow or signal change on SO4
Status register 5 (STS5) Status register 5 is a 4-bit register whose bits are used as shown below.
STS5
R/O
00H
Bits 0 and 1: These bits are always 0 and cannot be used. INTIN: Reflects in the input data on the INT pin. STBF: Strobe flag for the segment port (Set to 1 for 00 to 0F and to 0 for 10 to 1E.)
No. 4435-19/29
LC587008, 587006, 587004
Specifications
The electrical characteristics specified here are provisional and subject to change. Absolute Maximum Ratings at VSS = 0 V, Ta = 25C
Parameter Symbol VDD Maximum supply voltage VDD1 VDD2 VI (1) Maximum input voltage VI (2) VO (1) Maximum output voltage VO (2) VO (3) IO (1) IO (2) Output pin current IO (3) IO (4) IO (1) IO (2) Allowable power dissipation Operating temperature Storage temperature Pd max Topg Tstg Per pin K1 to K4, P1 to P4, M1 to M4, SO1 to SO4, A1 to A4 Total current for all pins K1 to K4, P1 to P4, M1 to M4, SO1 to SO4, A1 to A4, N1 to N4, Seg1 to Seg35 Allowed in the specified circuit (Figure 1), XTIN, CFIN S1 to S4, K1 to K4, P1 to P4, SO1 to SO4, A1to A4,RES, INT, TST, (With the K, P, M, SO and ports in input mode) Allowed in the specified circuit (Figure 1), XTOUT, CFOUT K1 to K4, P1 to P4, SO1 to SO4, A1 to A4, N1 to N4, CUP1, CUP2, Seg1 to Seg35, COM1 to COM4 (With the K, P, M, SO and A ports in output mode) Open drain specifications, N1 to N4 (N ch) N1 to N4 Conditions min -0.3 -0.3 -0.3 typ max +7.0 VDD VDD Unit V V V
Allowed up to the generated voltage -0.3 VDD + 0.3 V
Allowed up to the generated voltage
-0.3 -0.3 0 -10 0 -5
VDD + 0.3 +13 +15 0 5 0 70
V V mA mA mA mA mA mA
-70 500 -30 -55 +70 +125
QIP80 flat package
mW C C
Allowable Operating Ranges at VSS = 0 V, Ta = -30 to +70C
Parameter Symbol Conditions LCD unused specifications: VDD1 = VDD2 = VDD Static specifications: VDD1 = VDD2 = VDD Supply voltage VDD 1/2 bias specifications: VDD1 = VDD2 2 x 1/2 VDD 1/3 bias specifications: VDD1 2 x 1/3 VDD, VDD2 1/3 VDD Hold supply voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Operating frequency 1 Operating frequency 2 Operating frequency 3 Operating frequency 4 Operating frequency 5 Operating frequency 6 Operating frequency 7 Operating frequency 8 Operating frequency 9 VHD VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 fopg1 fopg2 fopg3 fopg4 fopg5 fopg6 fopg7 fopg8 fopg9 Voltage required to hold the contents of RAM and the registers* S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4, A1 to A4, INT, (With the K, P, M, SO and ports in input mode) RES pin min 2.0 2.0 2.8 2.8 2.0 0.7 VDD 0 0.75 VDD 0 0.75 VDD 0 32 XTIN/XTOUT crystal oscillator 37 60 190 CFIN/CFOUT CF specifications 190 190 190 100 190 typ max 6.0 6.0 6.0 6.0 VDD VDD 0.3 VDD VDD 0.25 VDD VDD 0.25 VDD 33 39 70 810 1200 2300 4200 1500 800 Unit V V V V V V V V V V V kHz kHz kHz kHz kHz kHz kHz kHz kHz
CFIN pin VDD = 2.0 to 6.0 V, 32 kHz VDD = 2.2 to 6.0 V. 38 kHz VDD = 2.2 to 6.0 V, 65 kHz VDD = 2.2 to 6.0 V VDD = 2.5 to 6.0 V VDD = 2.5 to 6.0 V VDD = 2.8 to 6.0 V VDD = 4.0 to 6.0 V, CFIN/CFOUT RC specifications VDD = 2.0 to 6.0 V, CFIN/CFOUT EXT specifications VDD = 3.0 to 6.0 V, O1/SO3 pins (in serial mode), Rising and falling edges on the input signals and clock waveform of the SO1/SO3 pins (in serial mode) must be 10 s or less.
Operating frequency 10
fopg10
DC
200
kHz
Note: In the state where the CF/RC oscillator and/or the crystal oscillator are completely stopped and the internal circuits are completely stopped.
No. 4435-20/29
LC587008, 587006, 587004 Electrical Characteristics at VDD = 2.5 to 3.2 V, VSS = 0 V, Ta = -30 to +70C
Parameter Symbol RIN1 A RIN1 B RIN1 C RIN1 D RIN2 A RIN2 B RIN2 C RIN2 D RIN3 RIN4 RIN5 RIN1 A Input resistance RIN1 B RIN1 C RIN1 D RIN2 A RIN2 B RIN2 C RIN2 D RIN3 RIN4 RIN5 Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output off leakage current Segment port output impedances [In CMOS output port mode] Output high level voltage Output low level voltage VOH (3) VOL (3) VOH (3) IOFF VOL (3) IOFF VOH (4) VOL (4) VOH (5) VOL (5) IOH = -100 A IOL = 100 A IOH = -100 A VOL = VSS IOL = 100 A VOH = VDD Seg1 to Seg35 VDD - 0.5 0.5 V V VOH (1) VOL (1) VOH (2) VOL (2) IOFF Conditions VIN = 0.2 VDD, low level hold transistor* Figure 2 VIN = VDD, pull-down resistor* Figure 2 VIN = 0.8 VDD, high level hold transistor* Figure 2 VIN = VSS, pull-up resistor* Figure 2 VIN = 0.2 VDD, the INT pin low level hold transistor VIN = VDD, The INT pin pull-down resistor VIN = 0.8 VDD, the INT pin high level hold transistor VIN = VSS, the INT pin pull-up resistor VIN = VDD, the RES pin pull-down resistor VIN = VSS, the RES pin pull-up resistor VIN = VDD, the TST pin pull-down resistor VIN = 0.2 VDD, low level hold transistor* Figure 2 VIN = VDD, pull-down resistor* Figure 2 VIN = 0.8 VDD, high level hold transistor* Figure 2 VIN = VSS, pull-up resistor* Figure 2 VIN = 0.2 VDD, the INT pin low level hold transistor VIN = VDD, the INT pin pull-down resistor VIN = 0.8 VDD, the INT pin high level hold transistor VIN = VSS, the INT pin pull-up resistor VIN = VDD, the RES pin pull-down resistor VIN = VSS, the RES pin pull-up resistor VIN = VDD, the TST pin pull-down resistor IOH = -500 A IOL = 1.0 mA IOH = -400 A IOL = 400 A VOH = 10.5 V N1 to N4 K1 to K4, P1 to P4, M1 to M4, SO1 to SO4, A1 to A4 (with the K, P, M, SO and A ports in output mode) N1 to 4 (open specifications), Figure 10 VDD = 2.5 V min 60 30 60 30 60 300 60 300 10 10 60 80 40 80 40 80 400 80 400 10 10 80 VDD - 0.5 0.5 VDD - 0.5 0.5 1.0 typ 300 150 300 150 300 1500 300 1500 30 30 250 300 150 300 150 300 1500 300 1500 30 30 250 max 1200 500 1200 500 1200 5000 1200 5000 50 50 1000 1200 500 1200 500 1200 5000 1200 5000 50 50 1000 Unit k k k k k k k k k k k k k k k k k k k k k k V V V V A
[In p-channel open-drain output port mode (See Figure 11.)] Output high level voltage Output off leakage current Seg1 to Seg35 VDD - 0.5 1.0 V A
[In n-channel open-drain output port mode (See Figure 11.)] Output low level voltage Output off leakage current [Static drive] Output high level voltage Output low level voltage Output high level voltage Output low level voltage IOH = -20 A, Seg1 to Seg35 IOL = 20 A IOH = -100 A, COM1 IOL = 100 A VDD - 0.2 0.2 VDD - 0.2 0.2 V V V V Seg1 to Seg35 0.5 1.0 V A
Note: For the 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4.
No. 4435-21/29
LC587008, 587006, 587004 Electrical Characteristics at VDD = 3.0 to 4.5 V, VSS = 0 V, Ta = -30 to +70C
Parameter Symbol RIN1 A RIN1 B RIN1 C RIN1 D RIN2 A RIN2 B RIN2 C RIN2 D RIN3 RIN4 RIN5 RIN1 A Input resistance RIN1 B RIN1 C RIN1 D RIN2 A RIN2 B RIN2 C RIN2 D RIN3 RIN4 RIN5 Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output off leakage current Segment port output impedances [In CMOS output port mode] Output high level voltage Output low level voltage VOH (3) VOL (3) VOH (3) IOFF VOL (3) IOFF VOH (4) VOL (4) VOH (5) VOL (5) VOH (4) VOL (4) VOH (5) VOM VOL (5) IOH = -100 A IOL = 100 A IOH = -100 A VOL = VSS IOL = 100 A VOH = VDD Seg1 to Seg35 VDD - 0.5 0.5 V V VOH (1) VOL (1) VOH (2) VOL (2) IOFF Conditions VIN = 0.2 VDD, low level hold transistor* Figure 2 VIN = VDD, pull-down resistor* Figure 2 VIN = 0.8 VDD, high level hold transistor* Figure 2 VIN = VSS, pull-up resistor* Figure 2 VIN = 0.2 VDD, the INT pin low level hold transistor VIN = VDD, The INT pin pull-down resistor VIN = 0.8 VDD, the INT pin high level hold transistor VIN = VSS, the INT pin pull-up resistor VIN = VDD, the RES pin pull-down resistor VIN = VSS, the RES pin pull-up resistor VIN = VDD, the TST pin pull-down resistor VIN = 0.2 VDD, low level hold transistor* Figure 2 VIN = VDD, pull-down resistor* Figure 2 VIN = 0.8 VDD, high level hold transistor* Figure 2 VIN = VSS, pull-up resistor* Figure 2 VIN = 0.2 VDD, the INT pin low level hold transistor VIN = VDD, the INT pin pull-down resistor VIN = 0.8 VDD, the INT pin high level hold transistor VIN = VSS, the INT pin pull-up resistor VIN = VDD, the RES pin pull-down resistor VIN = VSS, the RES pin pull-up resistor VIN = VDD, the TST pin pull-down resistor IOH = -500 A IOL = 1.0 mA IOH = -400 A IOL = 400 A VOH = 10.5 V N1 to N4 K1 to K4, P1 to P4, M1 to M4, SO1 to SO4, A1 to A4 (with the K, P, M, SO and A ports in output mode) N1 to 4 (open specifications), Figure 10 VDD = 3.0 to 4.0 V min 35 15 35 15 35 150 35 150 10 10 25 40 20 40 20 40 200 40 200 10 10 30 VDD - 0.5 0.5 VDD - 0.5 0.5 1.0 typ 200 80 200 80 200 800 200 800 30 30 130 200 80 200 80 300 800 200 800 30 30 130 max 800 300 800 300 800 3000 800 3000 50 50 500 800 300 800 300 800 3000 1200 3000 50 50 500 Unit k k k k k k k k k k k k k k k k k k k k k k V V V V A
[In p-channel open-drain output port mode (See Figure 11.)] Output high level voltage Output off leakage current Seg1 to Seg35 VDD - 0.5 1.0 V A
[In n-channel open-drain output port mode (See Figure 11.)] Output low level voltage Output off leakage current [Static drive] Output high level voltage Output low level voltage Output high level voltage Output low level voltage [1/2 bias drive] Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage IOH = -20 A IOL = 20 A IOH = -100 A IOH = -100 A IOL = 100 A IOL = 100 A COM1 to COM4 Seg1 to Seg35 VDD - 0.2 VDD - 0.2 VDD/2 - 0.2 VDD/2 + 0.2 0.2 0.2 V V V V IOH = -20 A, Seg1 to Seg35 IOL = 20 A IOH = -100 A, COM1 IOL = 100 A VDD - 0.2 0.2 VDD - 0.2 0.2 V V V V Seg1 to Seg35 0.5 1.0 V A
Note: For the 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4.
Continued on next page. No. 4435-22/29
LC587008, 587006, 587004
Continued from preceding page.
Parameter Symbol Conditions min typ max Unit
[1/3 bias drive: About 1/10 of the rating for VDD = 4.5 to 6.0 V] Supply leakage current Supply leakage current ILEK (1) ILEK (2) VDD = 3.0 V, Ta = 25C, Figure 3 VDD = 3.0 V, Ta = 50C, Figure 3 VDD = 3.0 V Input leakage current IOFF VIN = VDD VIN = VSS Output voltage 1 VDD1-(1) IDD 1-1 Supply current 1 IDD 1-2 IDD 2-1 Supply current 2 IDD 2-2 IDD 3-1 Supply current 3 IDD 3-2 Oscillator start voltage Oscillator hold voltage Oscillator start time Oscillator stability Oscillator start voltage Oscillator hold voltage Oscillator start time Oscillator start voltage Oscillator hold voltage Oscillator start time Oscillator start voltage Oscillator hold voltage Oscillator start time Oscillator correction capacitance VSTT VHOLD TSTT f VSTT VHOLD TSTT VSTT VHOLD TSTT VSTT VHOLD TSTT Cd VDD = 2.4 V VDD = 2.4 V TSTT 30 ms VDD = 2.4 V TSTT 30 ms VDD = 2.2 V VDD = 2.95 to 3.05 V TSTT 5 s S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4, A1 to A4, INT, RES (with the K, P, M, SO and A ports in input mode, and with open specifications for the INT and RES pins) 0.2 1.0 1.0 5.0 A A
1.0 -1.0 1.3 1.5 4.0 1.7 8.0 20 6.0 10 30 150 300 500 2.2
A A V A A V A A A V V s ppm V V s V V ms V V ms pF
VDD = 3.0 V, C1 = C2 = 0.1 F, VDD1 = VO, 1/2 bias, fopg = 32.768 kHz, Figure 4 VDD = 3.0 V, Ta = 25C VDD = 3.0 V, Ta = 50C VDD = 3.0 V, Ta = 25C VDD = 3.0 V, Ta = 50C VDD = 3.0 V, Ta = 25C VDD = 3.0 V, Ta = 50C TSTT 5 s Crystal oscillator specifications, using a 32 kHz crystal, Cg = 20 pF, CI 25 k, Figure 6 Crystal oscillator specifications, crystal: 32 kHz, Cg = 20 pF, CI = 25 k, HALT mode, Figure 6, LCD = 1/3 bias
Crystal oscillator specifications, crystal: 38 or 65 kHz, Cg = 10 pF, CI = 25 k, HALT mode, Figure 6, LCD = 1/3 bias CF oscillator specifications, CF: 400 kHz, Ccg = Ccd = 330 pF, HALT mode, Figure 7
2.0
6.0 5 3
Crystal oscillator specifications, using a 38 or 65 kHz crystal, XCg = 10 pF, CI 25 k, Figure 6 CF oscillator specifications, using a 400 kHz ceramic filter, Ccg = Ccd = 330 pF, Figure 7 CF oscillator specifications, using an 800 kHz ceramic filter, Ccg = Ccd = 220 pF or 100 pF, Figure 7
2.4 2.2 6.0 5 2.4 2.2 6.0 30 2.4 2.2 6.0 30 16 20 24
VDD = 3.0 V, XTOUT pin (built-in)
No. 4435-23/29
LC587008, 587006, 587004 Electrical Characteristics at VDD = 4.5 to 6.0 V, VSS = 0 V, Ta = -30 to +70C
Parameter Symbol RIN1 A RIN1 B RIN1 C RIN1 D RIN2 A Input resistance RIN2 B RIN2 C RIN2 D RIN3 RIN4 RIN5 Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output off leakage current Segment port output impedances [In CMOS output port mode] Output high level voltage Output low level voltage VOH (3) VOL (3) VOH (4) IOFF VOL (4) IOFF VOH (4) VOL (4) VOH (6) VOL (6) VOH (4) VOL (4) VOH (6) VOM2-1 VOL (6) VOH (4) VOM1-1 VOM1-2 Output low level voltage Output high level voltage VOL (4) VOH (6) VOM2-1 VOM2-2 Output low level voltage VOL (6) IOH = -500 A IOL = 500 A IOH = -500 A VOL = VSS IOL = 500 A VOH = VDD IOH = -40 A IOL = 40 A IOH = -400 A IOL = 400 A IOH = -40 A IOL = 40 A IOH = -400 A IOH = -400 A IOL = 400 A IOL = 400 A IOH = -40 A IOH = -40 A IOL = 40 A IOL = 40 A IOH = -400 A IOH = -400 A IOL = 400 A IOL = 400 A COM1 to COM4 VDD - 0.2 2 VDD/3 - 0.2 VDD/3 - 0.2 2 VDD/3 + 0.2 VDD/3 + 0.2 0.2 Seg1 to Seg35 VDD - 0.2 2 VDD/3 - 0.2 VDD/3 - 0.2 2 VDD/3 + 0.2 VDD/3 + 0.2 0.2 COM1 to COM4 Seg1 to Seg35 VDD - 0.5 VDD - 0.2 0.5 V V VOH (1) VOL (1) VOH (2) VOL (2) IOFF Conditions VIN = 0.2 VDD, low level hold transistor* Figure 2 VIN = VDD, pull-down resistor* Figure 2 VIN = 0.8 VDD, high level hold transistor* Figure 2 VIN = VSS, pull-up resistor* Figure 2 VIN = 0.2 VDD, the INT pin low level hold transistor VIN = VDD, The INT pin pull-down resistor VIN = 0.8 VDD, the INT pin high level hold transistor VIN = VSS, the INT pin pull-up resistor VIN = VDD, the RES pin pull-down resistor VIN = VSS, the RES pin pull-up resistor VIN = VDD, the TST pin pull-down resistor IOH = -5.0 mA IOL = 10.0 mA IOH = -1.0 mA IOL = 2.0 mA VOH = 10.5 V N1 to N4 min 30 10 30 10 30 100 30 100 10 10 20 VDD - 0.5 0.5 VDD - 0.5 VDD - 0.2 0.2 0.5 1.0 typ 120 50 120 50 120 500 120 500 30 30 70 max 500 200 500 200 500 2000 500 2000 50 50 300 Unit k k k k k k k k k k k V V V V A
K1 to K4, P1 to P4, M1 to M4, SO1 to SO4, A1 to A4 (with the K, P, M, SO and A ports in output mode), N1 to N4 (open specifications) Figure 10
[In p-channel open-drain output port mode (See Figure 11.)] Output high level voltage Output off leakage current Seg1 to Seg35 VDD - 0.5 VDD - 0.2 1.0 V A
[In N-channel open-drain output port mode (See Figure 11.)] Output low level voltage Output off leakage current [Static drive] Output high level voltage Output low level voltage Output high level voltage Output low level voltage [1/2 bias drive] Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage [1/3 bias drive] Output high level voltage V V V V V V V V Seg1 to Seg35 VDD - 0.2 0.2 VDD - 0.2 VDD/2 - 0.2 VDD/2 + 0.2 0.2 V V V V V Seg1 to Seg35 VDD - 0.2 0.2 VDD - 0.2 0.2 V V V V Seg1 to Seg35 0.2 0.5 1.0 V A
COM1
Output middle level voltage
Output middle level voltage
Note: For the 24 pins S1 to S4, K1 to K4, P1 to P4, M1 to M4, SO1 to SO4 and A1 to A4.
Continued on next page. No. 4435-24/29
LC587008, 587006, 587004
Continued from preceding page.
Parameter Symbol IOP-1 IOP-2 Operating current IOP-3 IOP-4 IOP-5 IOP-6 IOP-7 Supply leakage current Supply leakage current ILEK (1) ILEK (2) Conditions VDD = 3 V, Ta = 25C, 32 kHz crystal oscillator, LCD = 1/3 bias, Figure 6 VDD = 5 V, Ta = 25C, 32 kHz crystal oscillator, LCD = 1/3 bias, Figure 6 VDD = 3 V, Ta = 25C, 400 kHz, CF oscillator, Figure 6 VDD = 5 V, Ta = 25C, 400 kHz, CF oscillator, Figure 6 VDD = 3 V, Ta = 25C, 1 MHz, CF oscillator, Figure 6 VDD = 5 V, Ta = 25C, 1 MHz, CF oscillator, Figure 6 VDD = 5 V, Ta = 25C, 4 MHz, CF oscillator, Figure 6 VDD = 6.0 V, Ta = 25C, Figure 3 VDD = 6.0 V, Ta = 50C, Figure 3 VDD = 6.0 V Input leakage current IOFF VIN = VDD VIN = VSS Output voltage 2 Output voltage 3 VDD1-(2) VDD1-(3) VDD2-(3) IDD 1-1 Supply current 1 IDD 1-2 IDD 2-1 Supply current 2 IDD 2-2 IDD 3-1 Supply current 3 IDD 3-2 IDD 4-1 Supply current 4 IDD 4-2 IDD 5-1 Supply current 5 IDD 5-2 IDD 6-1 Supply current 6 IDD 6-2 Oscillator correction capacitance Cd S1 to S4, K1 to K4, M1 to M4, SO1 to SO4, A1 to A4, INT, RES (with the K, P, M, SO and A ports in input mode and with open specifications for the INT and RES pins) VDD1 = VO VDD1 = VO, VDD2 = VO min typ 20 40 240 620 350 850 1700 0.2 1.0 max 30 60 300 780 480 1200 2500 1.0 5.0 Unit A A A A A A A A A A 1.0 -1.0 2.4 1.4 3.1 2.5 1.67 3.33 15 2.6 1.8 3.5 30 50 15 30 50 400 600 600 450 650 700 500 700 750 700 900 1000 16 20 24 A A V V V A A A A A A A A A A A A pF
VDD = 5.0 V, C1 = C2 = 0.1 F, Figure 4, 1/2 bias, fopg = 32.768 kHz VDD = 5.0 V, C1 = C2 = 0.1 F, Figure 4, 1/3 bias, fopg = 32.768 kHz VDD = 5.0 V, Ta = 25C VDD = 5.0 V, Ta = 50C VDD = 5.0 V, Ta = 25C VDD = 5.0 V, Ta = 50C VDD = 5.0 V, Ta = 25C VDD = 5.0 V, Ta = 50C VDD = 5.0 V, Ta = 25C VDD = 5.0 V, Ta = 50C VDD = 5.0 V, Ta = 25C VDD = 5.0 V, Ta = 50C VDD = 5.0 V, Ta = 25C VDD = 5.0 V, Ta = 50C
Crystal oscillator specifications, crystal: 32 kHz Cg = 20 pF, C1 = 25 k, HALT mode, Figure 6, LCD = 1/3 bias Crystal oscillator specifications, crystal: 38 or 65 kHz, Cg = 10 pF, C1 = 25 k, HALT mode, Figure 6, LCD = 1/3 bias CF oscillator specifications, CF: 400 kHz, Ccg = Ccd = 330 pF, HALT mode, Figure 7
CF oscillator specifications, CF: 1000 kHz, Ccg = Ccd = 100 pF, HALT mode, Figure 8 or 220 pF
CF oscillator specifications, CF: 2000 kHz, Ccg = Ccd = 33 pF, HALT mode, Figure 8
CF oscillator specifications, CF: 4000 kHz, Ccg = Ccd = 33 pF, HALT mode, Figure 8
VDD = 5.0 V, XTOUT pin (built-in)
No. 4435-25/29
LC587008, 587006, 587004
Figure 1-1 Oscillator Circuit (XT pins)
Figure 1-2 Oscillator Circuit (CF pins)
Figure 2 S, K, P, M, SO and A Port Input Circuit Configuration Recommended Ceramic Filters
Manufacturer Item Frequency 400 kHz 800 kHz 1 MHz 2 MHz 4 MHz CSB400P CSB800J CSB1000J CSA2.00MG, CST2.00MG CSA4.00MG, CSA4.00MGW Murata Mfg. Co., Ltd. Catalog No. Ccg (pF) 330 220 220 Ccd (pF) 330 220 220 KBR-400B KBR-800H KBR-1000H/Y KBR-2.0MS KBR-4.0MSA/MCA, KBR-4.0MKS/MWS Kyocera Corporation Catalog No. Ccg (pF) 330 100 100 33 Ccd (pF) 330 100 100 33
33 (built-in) 33 (built-in) 33 (built-in) 33 (built-in)
33 (built-in) 33 (built-in)
* * * * * * * * * * *
Figure 3 Supply Leakage Test Circuit
Stopped state S-port input resistors: on state I/O ports: output mode, all data values high RES and INT pins: built-in resistor specifications, open state Currents due to external components connected to the LCD ports are not included. Crystal frequency: between 32 and 65 kHz CF frequency: 200 kHz to 4 MHz Crystal frequency: 32 kHz C1, C2 and C3: 0.1 F Figures 4 and 5 LCD ports: open CF frequency: 200 kHz to 4 MHz
Figure 4 Output Voltage Test Circuit
No. 4435-26/29
LC587008, 587006, 587004
Figure 5 Output Voltage Test Circuit
Figure 6 Supply Current Test Circuit
Figure 7 Supply Current Test Circuit
Figure 8 Supply Current Test Circuit
Figure 9 Supply Current Test Circuit
Figure 10 Supply Current Test Circuit
Figure 11 Segment Pin Open Drain Circuit Configurations
No. 4435-27/29
LC587008, 587006, 587004
Figure 12 Sample RC Oscillator Frequency Characteristics
Figure 14 Timer 1 and Timer 2 External Clock Input Timing (external clock mode, pins M3 and M4)
Figure 13 Serial I/O Timing (in external clock mode)
Figure Initial Reset Timing
No. 4435-28/29
LC587008, 587006, 587004
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1995. Specifications and information herein are subject to change without notice. PS No. 4435-29/29

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